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1 of 24 rf micro devices, inc. 7628 thorndike road greensboro, nc 27409, usa tel (336) 664 1233 fax (336) 664 0454 http://www.rfmd.com product description features optimum technology matching? applied si bjt si bi-cmos gainp/hbt gaas hbt sige hbt gan hemt gaas mesfet si cmos sige bi-cmos ordering information to antenna voltage reg 2.4 ghz direct conversion transceiver modem internal 32 khz clock sleep control bluetooth baseband with cvsd fast locking pll up to 2 mbs rom hci firmware audio codec interface sram data gpio usb power management uart arm7tdmi processor ? usb full speed system i/o codec master or slave 2.3 ~ 3.63 v crystal or reference clock siw3000 ultimateblue? radio processor the siw3000 ultimateblue? radio processor is a recent innovation for bluetooth? wireless technology. it combines the industry's best performing and most highly integrated radio design with an armtdmi? processor using cmos technology. the siw3000 uses direct conversion (zero-if) architecture. this allows digital filtering for excellent interference rejection as compared to low if solutions and also results in fewer spurious responses. the lower-layer protocol stack software is integrated into the on-chip rom. optional external flash memory is also supported. the siw3000 is compliant with bluetooth specification 1.2 features. the device is available in multiple packages and bare die form with a guaranteed operating temperature range from -40c to +85c and an extended high temperature range to +105c. single-chip ic with 2.4 ghz transceiver, baseband processor, and on-chip protocol stack for bluetooth? wireless technology compliant with bluetooth specification 1.2 features. low cost 0.18 m cmos process technology. 1.8 v analog and digital core voltages; 1.62 v to 3.63 v external i/o interface voltage. typical -85 dbm receiver sensitivity, +2 dbm transmitter power for up to 100 meters nominal range. on-chip vco and pll support multiple gsm/gprs and cdma cellular reference clock frequencies. hardware agc dynamically adjusts receiver performance in changing environments. integrated 32-bit armtdmi? processor for extended features. full piconet connectivity with support for up to 7 active and 8 parked slaves. scatternet compatible with microsoft? hid devices. supports three sco voice channels. channel quality driven data rate (cqddr) controls mu lti-slot packets to minimize packet overhead and maximize data throughput. option for bluetooth + wi-fi coexistence. applications mobile phones. notebook and desktop pcs. cordless headsets. personal digital assistants (pdas). computer accessories, peripherals, and wireless printers/ keyboards/mice). siw3000 ultimateblue? radio processor 0 60 0049 r01drf siw3000 radio processor ds 9 block diagram september 30, 2004
2 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds radio features direct-conversion architecture with no external if filter or vco resonator components. single ended rf i/o reduces system bill of materials (bom) costs by eliminating the need to use external balun and switch circuits. on-chip vco and pll support multiple gsm, cdma, gprs standard reference clock frequencies. low out-of-band spurious emission transmitter prevents blocking of sensitive mobile phone rf circuits. no tuning during production. internal temperature compensation circuit stabilizes performance across wide operating temperature. fast settling synthesizer reduces power consumption. up to 100 meter operating range in standard configuration without using an external pa. baseband features arm7tdmi processor core running at 16 mhz. digital gfsk modem for maximum performance and lower packet error rate. on-chip cvsd conversion with hardware based gain adjustments to enhance audio quality. sleep control interface for low power operation modes. software execution from rom or external flash memory. standard protocol stack features full piconet connectivity with support for up to 7 active and 8 parked slaves. able to establish up to 3 sco connections. scatternet capable and compatible with microsoft hid devices. standard bluetooth test modes. low power connection states supported with hold, sniff, and park modes. additional protocol stack features channel quality driven data rate (cqddr) optimizes data transfer rate in noisy or weak signal environments audio (sco) routing over hci interface for voip applications. support for bluetooth + wi-fi coexistence technology. verified compatibility with multiple upper-layer stack vendors. extensive vendor specific hci commands enables hardware specific controls. optional upper-layer stack and profiles can be licensed and integrated into the ic. bluetooth 1.2 features adaptive frequency hopping (afh). faster connections. lmp improvements. external system interfaces host hci transport (h:2 usb) the usb device interface provides a physical transport between the siw3000 and the host for the transfer of bluetooth control signals and data. this transport layer is fully compliant with section h:2 of the bluetooth specification with all end points supported. the siw3000 usb interface encompasses three i/o signals: usb_dpls, usb_dmns, and usb_dpls_pullup. if the usb transport is not used, the usb_dpls and usb_dmns pins should be grounded to reduce current consumption.
3 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds host hci transport (h:4 uart) the high speed uart interface provides the physical transport between the siw3000 and the application host for the transfer of bluetooth control signals and data compliant to section h:4 of the bluetooth specification. the table below shows the supported baud rates. the default baud rate is 115,200, but can be configured depending on the application. host hci transport (h:5 3-wire uart) to reduce the number of signals and increase reliability of the hci uart interface, a 3-wire uart using either the bluetooth h:5 or bcsp protocol is supported. the selection between h:4, h:5, and bcsp is done automatically by the siw3000, or can be set in nvm. audio codec interface the siw3000 supports direct interface to an external audio codec or pcm host device. the interface is easily config- ured to support: standard 64-khz pcm clock rate. up to 2-mhz clock rates with support for multi-slot handshakes and synchronization. either master or slave (motorola ssi) mode. configuration of the codec interface is done by the firmware during boot-up by reading non-volatile memory (nvm) parameters. the following are examples of supported codec modes: generic 64-khz audio codec (e.g., oki msm-7702). motorola mc145481 or similar codec as master. qualcomm msm chip set audio port. gsm/gprs baseband ic audio ports. programmable i/o (pio) up to twenty-nine (29) programmable io (pio) ports are available for customer use in the siw3000. three of these pios are dedicated and the remaining pios are shared with other functions. availability of pios will depend on system config- uration. the table below identifies the all twenty-nine pios and their usage. the pio ports can be set to input or output. reading, writing, and controlling the pio pins by the host application software can be done via vendor specific hci com- mands. siw3000 radio processor hci uart parameters required host setting number of data bits 8 parity bit no parity stop bit 1 stop bit flow control rts/cts host flow-off response requirem ent from the siw3000 8 bytes siw3000 ic flow-off response requirement from host 2 bytes supported baud rates 9.6k, 19.2k, 38.4k, 57.6k, 115.2k a , 230.4k, 460.8k, 500k, 921.6k, 1m, 1.5m, 2m a.default baud rate. siw3000 radio processor hci 3-wire uart parameters required host setting number of data bits 8 parity bit even stop bit 1 stop bit error detection slip and checksum sleep modes shallow and deep
4 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds external memory interface the ultimate 3000 radio processor is a true single chip device and does not require additional memory for standard below hci protocol functions. an external memory interface is available for adding optional memory. if external flash memory will be used, the read access time of the device must be 100 ns or less. the external memory interface permits connection to flash and sram devices. the interface has an 18-bit address bus and a 16-bit data bus for a total addressable memory of 512 kb. in certain embedded applications, both sram and flash can be installed by using the high order address bit as an alternate chip select. external eeprom controller and interface this interface is intended for use with rom-based solutions. the eeprom is not required for configurations with exter- nal flash. the eeprom is the non-volatile memory (nvm) in the system and contains the system configuration parame- ters such as the bluetooth device address, the codec type, as well as other parameters. these default parameters are set at the factory, and some parameters will change depending on the system configuration. optionally, the non-volatile memory parameters can be downloaded from the host processor at boot up eliminating the need for eeprom. please consult the application support team for details. the eeproms should have a serial i 2 c interface with a minimum size of 2 kbits and 16-byte page write buffer capabilities. power management the host_wakeup and ext_wake signals are used for power management. host_wakeup is an output signal used to wake up the host. ext_wake is an input signal used by the host to wake up the siw3000 radio processor from sleep mode. for more information on the usage of host_wake and ext_wake, please refer to rfmd application note 62 0031. pio# shared i/o sampled at reset pio# shared i/o sampled at reset 0 none yes 15 pcm_out no 1 none yes 16 pcm_in no 2 none yes 17 pcm_clk no 3 d[8] no 18 pcm_sync no 4 d[4] no 19 ext_wake no 5 d[5] no 20 host_wakeup no 6 d[6] no 21 uart_rxd no 7 d[7] no 22 uart_txd no 8 pwr_reg_en no 23 uart_cts no 9 d[15] no 24 uart_rts no 10 we_n no 25 a[18] no 11 a[16] no 26 tx_rx_switch no 12 a[17] no 27 d[9] no 13 a[11] no 28 d[10] no 14 usb_dpls_pullup no signal description address a[1] - a[18] 18-bit address bus data d[0] - d[15] 16-bit data bus fcs_n chip select oe_n output enable we_n write enable
5 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds general system requirements system reference clock the siw3000 chip can use either an external crystal or a reference clock as the system clock input. the supported fre- quencies are: 9.6 mhz, 12 mhz, 12.8 mhz, 13 mhz, 14.4 mhz, 15.36 mhz, 16 mhz, 16.8 mhz, 19.2 mhz, 19.68 mhz, 19.8 mhz, 26 mhz, 32 mhz, 38.4 mhz, and 48 mhz. the default reference frequency can be selected by setting the proper system configuration parameter in the non-volatile memory (nvm). if the usb hci transport will be used, the ref- erence clock must be 32 mhz. the system reference crystal/clock must have accuracy of 20 ppm or better to meet the specification of bluetooth. to facilitate design and production, the siw3000 processor incorporates internal crystal calibration circuits to allow factory calibration of initial crystal frequency accuracy. low power clock for the bluetooth low power clock, a 32.768-khz crystal may be used to drive the siw3000 oscillator circuit, or alterna- tively, a 32.768-khz reference clock signal can be used instead of a crystal. if the lowest power consumption is not required during low-power modes such as sniff, hold, park, and idle modes, the 32.768-khz crystal may be omitted in the design. if the 32.768-khz clock source will be used, the clock source should be connected to the clk32_in pin and must meet the following requirements: for ac-coupled via 100 pf or greater (peak-to-peak voltage): 400 mv p-p < clk32_in < v dd_c for dc-coupled: clk32_in minimum peak voltage < vil clk32_in maximum peak voltage > vih where v il = 0.3 * v dd_c where v ih = 0.7 * v dd_c for both cases, the signal is not to exceed: -0.3 v < clk32_in < v dd_c + 0.3 v also, the clk32_out pin must be coupled to v dd_p or gnd through a 100 nf capacitor. power supply description the siw3000 radio processor operates at 1.8 v core voltage for internal analog and digital circuits. the chip has inter- nal analog and digital voltage regulators simplifying power supply requirements to the chip. the internal voltage regula- tors can be supplied directly from a battery or from other system voltage sources. optionally, the internal regulators can be by-passed if 1.8 v regulated source is available on the system. note: both regulators can be bypassed if external regulation is desired. when bypassing the analog regulator, the vbatt_ana and vcc_out pins must be tied together and the external analog voltage (1.8 v) should be applied to the vbatt_ana pin. when bypassing the digita l regulator, the vbatt_dig pin should be left unconnected and the external digital voltage (1.8 v) shou ld be applied to vbb_out pin. the power for the i/os is taken from a separate source (v dd_p ). v dd_p can range from 1.62 to 3.63 volts to maintain compatibility with a wide range of peripheral devices. please check the pin list for the exact pins that are powered from the v dd_p source. power for the usb circuits is taken from a separate source (v dd_usb ). function internal analog regulator internal digital regulator regulator input pin v batt_ana = 2.3 to 3.63 v v batt_dig = 2.3 to 3.63 v regulator output pin v cc_out = 1.8 v v dd_c = 1.8 v table 1. internal regulator used function analog core circuits digital core circuits circuit voltage supply pin v cc = 1.8 v v dd_c = 1.8 v table 2. internal regulator bypassed
6 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds rf i/o description the siw3000 processor employs single-ended rf input and output pins for reduced external components. in typical class-2 (0 dbm nominal) applications, simple lc network matching circuits will be required to combine the two ports into a single antenna port and provide impedance matching. please refer to the rf impedance table and the application cir- cuits for values and matching circuit examples. the siw3000 can be used to design class-1 (+20 dbm) products with the addition of power amplifier circuits. control signals are available to facilitate the design of the external pa circuit. reset the siw3000 processor can be reset by asserting the reset_n signal to the chip (active low). upon applying power, the reset_n must be asserted until voltage supply and internal voltage regulators have stabilized. a simple rc circuit can be used to provide the power-on reset signal to the siw3000. on-chip memory the siw3000 radio processor integrates both sram and rom. the rom is pre-programmed with bluetooth protocol stack software (hci software) and boot code that executes automatically upon reset. the boot code serves to control the boot sequence as well as to direct the execution to the appropriate memory for continued operation. configuration selection hci transport interface selection the hci transport (usb or uart) is selected on power up by sampling pio2. if uart is selected, the selection of the particular uart transport (h:4 or h:5) is performed automatically by the software. reference frequency selection the siw3000 radio processor is designed to operate with multiple reference frequencies. during boot up the processor samples pio pins to determine the default reference frequency. if the usb transport is selected, the default reference frequency will always be 32 mhz. if the uart transport is selected, the reference frequency setting will be set according to the following table: application software memory selection the siw3000 can support application (protocol stack) software execution from internal rom and external flash mem- ory. to run from internal rom, d[9] and d[10] pins must be connected together as shown in the application circuit sec- tion of this document. to run from external flash memory the flash must be connected as shown in the application circuit diagram and contain valid application code. if an external memory does not have valid program data, the device enters a download mode in which a valid program may be loaded into the external memory through a sequence of com- mands over the hci transport layer. value (pio 2) description 0uart 1usb pio 1 usb_dpls_pullup reference frequency selection 1don't care reference frequency per nvm system configu- ration setting, or if nvm is not set, defaults to 32 mhz. 0 0 13 mhz 0 1 26 mhz
7 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds pin description the following table provides detailed listings of pin descriptions arranged by functional groupings. name pad type ball description radio (power from vcc) rf_in analog a2 rf signal input into the receiver. rf_out analog a4 rf signal out put from the transmitter. vtune analog a6 pin for reference pll loop filter, onl y used if reference frequency is not integer multiples of 4 mhz. chg_pump analog f1 pin for rf loop filter. xtal_n analog a7 system clock crystal negativ e input. if a reference clock is used, this pin should be left unconnected. xtal_p/clk analog b7 system clock crystal positive input or reference clock input. idac analog b1 power control to external power amplif ier. this output provides a variable current source that can be used to control the external power amp. leave unconnected if not used. vrefp_cap analog c1 decoupling capacitor for internal a/d converter voltage reference. vrefn_cap analog c2 decoupling capacitor for internal a/d converter voltage reference. low power oscillator and reset (power from vdd_p) clk32k_in analog k10 for crystal or ex ternal clock input (32.768 khz). clk32k_out analog l11 drive for crystal. reset_n analog c6 system level reset (active low). power control interface (power from vdd_p) pwr_reg_en/pio[8] cmos bi-directional g1 enable for an external voltage regulator. programmable active high or active low. also used as pio[8], which is the default mode until the appro- priate configuration bit is set. tie to ground if not used. tx_rx_switch cmos output j9 output signal used to indicate the curr ent state of the radio. this could be used as a direction control for an exte rnal power amplifier.the polarity is programmable with the default set as: low = transmit mode high = receive mode table 3. siw3000 radio processor pin list
8 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds programmable i/o (power from vdd_p) pio[0] cmos bi-directional k5 programmable input/output. needs to be low until internal rese t goes high or tie to ground if not used. pio[1] cmos bi-directional b8 programmable input/output. sampled following reset for frequency selection: if uart transport is selected and pio[1] = 0, frequency is selected by the state of usb_dpls_pullup pin. if uart transport is selected and pio[1] = 1, frequency is selected by nvm parameter. default for proper ua rt operation will be configured as 32 mhz. if usb transport is selected, pio[ 1] is ignored and the frequency will be configured as 32 mhz. pio[2] cmos bi-directional j10 programmable input/output. sampled following reset for transport selection: pio[2] = 0, selects uart transport pio[2] = 1, selects usb transport pcm interface (power from vdd_p) pcm_in cmos output e10 pcm data to the pcm codec. pcm_out cmos input f10 pcm data from t he remote device. normally an input. pcm_clk cmos bi-directional g10 pcm synchronous data clock to the remote device. normally an output. input for motorola ssi slave mode. pcm_sync cmos bi-directional h10 pcm synchronization data strobe to t he remote device. normally an out- put. input for motorola ssi slave mode. uart interface (power from vdd_p) uart_rxd cmos input k7 uart receive data. uart_txd cmos output k3 uart transmit data. uart_cts cmos input k6 uart flow control clear to send. uart_rts cmos output g9 uart flow control ready to send. ext_wake cmos input f3 wake up signal from host. host_wakeup cmos output g2 wake up signal to host. usb interface (power from vdd_usb) usb_dpls analog k9 usb differ ential pair positive signal. usb_dmns analog k8 usb diff erential pair negative signal. usb_dpls_ pullup cmos bi-directional j8 output signal for controlling the on/ off of the pull-up of the usb_dpls line. for uart transport, this pin is sampled following reset for frequency selection if pio[1] = 0: usb_dpls_ pullup = 0, selects 13 mhz usb_dpls_ pullup = 1, selects 26 mhz name pad type ball description table 3. siw3000 radio processor pin list (continued)
9 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds external memory interface (power from vdd_p) a[18] a[17]/eeprom_scl a[16]/eeprom_sda a[15] a[14] a[13] a[12] a[11] a[10] a[9] a[8] a[7] a[6] a[5] a[4] a[3] a[2] a[1] cmos output l1 g3 h1 a8 h2 c9 h3 j1 k4 j7 l4 a11 l7 f9 e11 e9 d11 d9 address lines. note: a[17] and a[16] can be used to support an optional external serial eeprom when using the internal rom in place of the external flash memory. d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8]/pio[3] d[7]/pio[7] d[6]/pio[6] d[5]/pio[5] d[4]/pio[4] d[3] d[2] d[1] d[0] cmos bi-directional with internal pull-down b11 c10 c11 b10 g11 h11 h9 j2 j11 d10 l3 l2 j4 j3 k2 k1 data lines. note : d[4] through d[8] can be used as programmable i/o when using the internal rom in place of the external flash memory. note : connect d[9] to d[10] to use internal rom. oe_n cmos output a10 output enable for external memory (active low). we_n/eeprom_wp cmos output k11 write enable for external memory (active low). note: can be used to support an optional external serial eeprom when using the internal rom in place of external flash memory. fcs_n cmos output b9 chip select for external memory (active low). power and ground vbatt_ana power d3 positive supply to internal analog voltage regulator. vbatt_dig power l8 positive supply to internal digital voltage regulator. vcc_out power d1 regulated output from internal analog voltage regulator. vdd_p power f11 l5 positive supply for digital input/output ports including peripheral interface, external memory interface, and uart interface. vdd_usb power l10 positive supply for usb interface. vdd_c power a9 l6 positive supply for digital circuitry or output of internal digital voltage. vcc power a1 b6 c4 c5 e1 e3 positive supply for rf and analog circuitry. vss_p gnd c7 j5 ground connections for digital input/ output ports including peripheral interface, external memory interface, and uart interface. vss_c gnd c8 j6 ground connections for internal digital circuitry. vss_usb gnd l9 ground connections for usb interface. name pad type ball description table 3. siw3000 radio processor pin list (continued)
10 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds gnd gnd a3 a5 b2 b3 b4 b5 c3 d2 e2 f2 ground connections for rf and analog circuitry. name pad type ball description table 3. siw3000 radio processor pin list (continued)
11 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds system specifications absolute maximum ratings recommended oper ating conditions esd rating note: this device is a high performance rf integrated circuit with an esd rating of 2,000 volts (hbm conditions per mi l-std-883, meth od 3015). handling and assembly of this device should onl y be done using appropriate esd controlled processes. electrical characteristics dc specification (t op =+25 c, v dd_p =3.0 v) ac characteristics (t op = +25 c, v dd_p =3.0 v, c load =15 pf ) parameter description min max unit v cc analog circuit suppl y voltage -0.3 3.63 v v dd_io i/o supply voltage -0.3 3.63 v v batt_ana analog regulator supply voltage -0.3 3.63 v v batt_dig digital regulator supply voltage -0.3 3.63 v t st storage temperature -55 +125 c rf max maximum rf input level ? +5 dbm absolute maximum ratings indicate limits beyond which the us eful life of the device may be impaired or damage may occur. parameter description min max unit t op operating temperature (industrial grade) -40 +85 c t eop extended operating temperature -40 +105 c v batt_ana unregulated supply voltage into in ternal analog regulator 2.3 3.63 v v batt_dig unregulated supply voltage into inte rnal digital regulator 2.3 3.63 v v cc regulated supply voltage directly into analog circuits 1.71 1.89 v v dd_c regulated supply voltage directly in to digital circuits 1.62 2.16 v v dd_p digital interface i/o supply voltage 1.62 3.63 v v dd_usb regulated supply voltage for usb interface to meet usb specification requirements 3.1 3.63 v symbol description rating esd esd protection - all pins 2000 v symbol description min. typ. max. unit v il input low voltage gnd-0.1 ? 0.3 . v dd_p v v ih input high voltage 0.7 . v dd_p ? v dd_p v v ol output low voltage gnd ? 0.2 . v dd_p v v oh output high voltage 0.8 . v dd_p ? v dd_p v i oh output high current ? 1 ? ma output high current (ball j8) ? 4 ? ma i ol output low current ? 1 ? ma output low current (ball j8) ? 4 ? ma i ili input leakage current ? 1 ? a symbol description max. unit t r rise time 30 ns t f fall time 24 ns
12 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds current consumption (t op = +25 c, v batt =3.0 v using internal regulators) digital regulator specification (t op = 25 c) radio specification rf impedances operating mode average unit standby 25 a parked slave, 1.28 sec. interval 160 a page/inquiry scan, 1.28 sec. interval 1.5 ma acl connection, sniff mode, 100 ms interval 1.2 ma acl data transfer 720 kbps, dh5 continuous packets 60 ma sco connection, hv1 packets 60 ma sco connection, hv3 packets 32 ma parameter description min typ max unit output voltage (i out = 10 ma) 1.62 1.85 2.16 v line regulation (i out = 0 ma, v batt_dig = 2.3 v to 3.63 v) ?8.0 ?mv load regulation (i out = 3 ma to 80 ma) ?9.0 ?mv dropout voltage (i out = 10 ma) ? ? 250 mv output maximum current ? ? ? 80 ma quiescent current ? ? 10 ? a ripple rejection f ripple = 400 hz ?40 ?db parameter description min typ max unit vco operating range frequency 2402 ? 2480 mhz pll lock time ? ? 55 100 s parameter a a.the impedance values are for typical samples in 96-pin vfbga package. description min typ max unit rf impedance tx on ? 769//1.1 ? ? /pf tx off ? 26//2.4 ? ? /pf rx on ? 142//1.8 ? ? /pf rx off ? 45.7//0 ? ? /pf
13 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds receiver specification (v batt = 3.3 v, v cc =int. analog reg. output, nominal bluetooth test conditions) note: nominal and extreme bluetooth test conditions as defined by the bluetooth test and interoperability working group publishe d rf test specification 1.1. transmitter specification (v batt = 3.3 v, v cc = int. analog reg. output, nom. bluetooth test conditions) parameter description min typ max unit receiver sensitivity ber < 0.1% ? -85 -80 dbm maximum usable signal ber < 0.1% ? 0 ? dbm c/i co-channel (0.1% ber) co-channel selectivity ? 8 11 db c/i 1 mhz (0.1% ber) adjacent channel selectivity ? -4 0 db c/i 2 mhz (0.1% ber) 2nd adjacent channel selectivity ? -38 -35 db c/i 3 mhz (0.1% ber) 3rd adjacent channel selectivity ? -43 -40 db out-of-band blocking 30 mhz - 2000 mhz -10 ? ? dbm 2000 mhz - 2399 mhz -27 ? ? dbm 2498 mhz - 3000 mhz -27 ? ? dbm 3000 mhz - 12.75 ghz -10 ? ? dbm intermodulation max interferer level to maintain 0.1% ber, interference signals at 3 and 6 mhz offset. -39 -36 ? dbm receiver spurious emission 30 mhz to 1 ghz ? ? -57 dbm 1 ghz to 12.75 ghz ? ? -47 dbm parameter description min typ max units output rf transmit power at maximum power output level -2 +2 +6 dbm modulation index ? 0.28 0.306 0.35 ? initial carrier fre- quency accuracy ? -75 ? +75 khz carrier frequency drift one slot packet -25 ? +25 khz two slot packet -40 ? +40 khz five slot packet -40 ? +40 khz max drift rate ? ? 400 hz/s 20 db occupied bandwidth bluetooth specification ? ? 1000 khz in-band spurious emission 2 mhz offset ? -74 -55 dbm >3 mhz offset ? -74 -55 dbm out-of-band spurious emission 30 mhz to 1 ghz, operating mode ? -70 -55 dbm 1 ghz to 12.75 ghz, operating mode a a.except transmit harmonics. ? -70 -50 dbm 1.8 ghz to 1.9 ghz ? ? -62 dbm 5.15 ghz to 5.3 ghz ? ? -47 dbm
14 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds system requirements analog voltage supply requirements the siw3000 processor is designed for use with integrated low noise analog voltage regulators and is recommended for all applications. if necessary, the internal analog regulator can be bypassed. in situations where bypassing the internal analog regulator is required, the supply voltage to the analog circuit must satisfy the following requirements to preserve the rf performance characteristics. external reference requirements it is possible to provide a number of reference frequencies that are typical on most cellular phones directly into ball b7 (xtal_p/clk) of the device. the following reference frequencies (in mhz) can be used: 3.84, 9.6, 12, 12.8, 13, 14.4, 15.36, 16, 16.8, 19.2, 19.68, 19.8, 26, 32, 38.4, and 48 mhz. for other frequencies, please contact rfmd. reference crystal requirements many reference frequencies are supported by the device. if a crystal is used as the reference frequency source, the typ- ical required parameters are listed below: parameter description min max unit vcc analog supply voltage to al l vcc input pins 1.71 1.89 v minimum load current external regulator current 80 ? ma minimum ripple rejection at 400hz 40 ? db output noise integrated 10 hz to 80 khz noise ? 22 mv rms parameter description min max units phase noise 100 hz offset ? -100 dbc/hz 1 khz offset ? -120 dbc/hz 10 khz offset ? -140 dbc/hz drive level ac amplitude 0.5 v cc v p-p dc level a a.if dc-coupled, the external reference signal vo ltage must stay within this range at all times. 0.3 v cc v parameter description min typ max unit drive level ? ? ? 0.3 mw esr effective serial resistance a a.for 32-mhz crystal. ? ? 150 w c o holder capacitance b b.the actual values for c o and c l are dependent on the crystal manufacturer and can be compensated for by an internal crystal calibra- tion capability. ?35pf c l load capacitance b ?1218pf c m motional capacitance ? 6 ? ff
15 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds application circuit for external flash-based products c18 0.1uf l1 18nh u1 a1 b1 c1 c2 d1 d3 e1 e3 f1 g1 g2 g3 h1 h2 j1 j2 k1 l1 k2 l2 j3 k3 l3 j4 k4 l4 h3 k5 l6 k6 f3 l7 j7 k7 l8 j8 l9 k8 k9 l10 j9 l11 k10 k11 h9 j10 j11 h11 h10 g10 g11 f11 f10 f9 e11 e10 g9 d11 e9 d10 c11 d9 c10 b11 a11 b10 c9 a10 l5 b9 a9 b8 a8 c6 a7 b7 b6 a6 c5 a4 c4 a2 j5 c7 a3 a5 b2 b3 b4 b5 c3 c8 d2 e2 f2 j6 vcc idac vrefp_cap vrefn_cap vcc_out vbatt_ana vcc vcc chg_pump pwr_reg_en/pio[8] host_wakeup a[17]/eeprom_scl a[16]/eeprom_sda a[14] a[11] d[8]/pio[3] d[0] a[18] d[1] d[4]/pio[4] d[2] uart_txd d[5]/pio[5] d[3] a[10] a[8] a[12] pio[0] vdd_c uart_cts ext_wake a[6] a[9] uart_rxd vbatt_dig usb_dpls_pullup vss_usb usb_dmns usb_dpls vdd_usb tx_rx_switch clk32k_out clk32k_in we_n/eeprom_wp d[9] pio[2] d[7]/pio[7] d[10] pcm_sync pcm_clk d[11] vdd_p pcm_out a[5] a[4] pcm_in uart_rts a[2] a[3] d[6]/pio[6] d[13] a[1] d[14] d[15] a[7] d[12] a[13] oe_n vdd_p fcs_n vdd_c pio[1] a[15] reset_n xtal_n xtal_p/clk vcc vtune vcc rf_out vcc rf_in vss_p vss_p gnd gnd gnd gnd gnd gnd gnd vss_c gnd gnd gnd vss_c c19 0.1uf c2 1uf y1 xtl 32mhz 1 3 u2 2m or 4m flash e1 d1 c1 a1 b1 d2 c2 a2 b5 a5 c5 d5 b6 a6 c6 d6 e6 b2 g1 a4 f1 a3 b3 c3 d3 b4 c4 d4 f6 e2 h2 e3 h3 h4 e4 h5 e5 f2 g2 f3 g3 f4 g5 f5 g6 g4 h1 h6 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 oe we ce ry/by# nc nc nc reset# nc nc byte# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 vcc gnd gnd c4 0.1uf vcc vdd_p c16 dni r2, c16, and c17 are not required for 32mhz applications. for component values using other frequencies, refer to the reference design application note. c21 0.1uf c5 8.2pf c1 1uf c15 180pf r3 100k c20 0.1uf l4 4.7nh r1 47k vdd_p c10 1uf rf_in_out c6 8.2pf vbatt host interface in out fl1 shosin filter hmd846h 1 2 c7 8.2pf (external flash configuration) c14 22pf l6 2.7nh c12 2.7pf c11 2.7pf c8 18pf siw3000 c9 18pf c13 1.8pf l3 3.9nh vcc l5 3.3nh l2 3.3nh vdd_usb vcc vcc is the output from the internal voltage regulator. c3 0.1uf c17 dni r2 dni note: filter is not required to meet bt and fcc specifications but may be added if better out-of-band performance is desired.
16 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds application circuit for internal rom-based products vcc c11 2.7pf c20 0.1uf c1 1uf c10 1uf c3 0.1uf l5 3.3nh r2 dni siw3000 r2, c16, and c17 are not required for 32mhz applications. for component values using other frequencies, refer to the reference design application note. c5 8.2pf vdd_p vdd_usb u1 a1 b1 c1 c2 d1 d3 e1 e3 f1 g1 g2 g3 h1 h2 j1 j2 k1 l1 k2 l2 j3 k3 l3 j4 k4 l4 h3 k5 l6 k6 f3 l7 j7 k7 l8 j8 l9 k8 k9 l10 j9 l11 k10 k11 h9 j10 j11 h11 h10 g10 g11 f11 f10 f9 e11 e10 g9 d11 e9 d10 c11 d9 c10 b11 a11 b10 c9 a10 l5 b9 a9 b8 a8 c6 a7 b7 b6 a6 c5 a4 c4 a2 j5 c7 a3 a5 b2 b3 b4 b5 c3 c8 d2 e2 f2 j6 vcc idac vrefp_cap vrefn_cap vcc_out vbatt_ana vcc vcc chg_pump pwr_reg_en/pio[8] host_wakeup a[17]/eeprom_scl a[16]/eeprom_sda a[14] a[11] d[8]/pio[3] d[0] a[18] d[1] d[4]/pio[4] d[2] uart_txd d[5]/pio[5] d[3] a[10] a[8] a[12] pio[0] vdd_c uart_cts ext_wake a[6] a[9] uart_rxd vbatt_dig usb_dpls_pullup vss_usb usb_dmns usb_dpls vdd_usb tx_rx_switch clk32k_out clk32k_in we_n/eeprom_wp d[9] pio[2] d[7]/pio[7] d[10] pcm_sync pcm_clk d[11] vdd_p pcm_out a[5] a[4] pcm_in uart_rts a[2] a[3] d[6]/pio[6] d[13] a[1] d[14] d[15] a[7] d[12] a[13] oe_n vdd_p fcs_n vdd_c pio[1] a[15] reset_n xtal_n xtal_p/clk vcc vtune vcc rf_out vcc rf_in vss_p vss_p gnd gnd gnd gnd gnd gnd gnd vss_c gnd gnd gnd vss_c vdd_p vcc l1 18nh u2 eeprom 1 2 3 4 5 6 7 8 a0 a1 a2 gnd sda scl wp vcc c4 0.1uf vcc c19 0.1uf (internal rom configuration) vcc is the output from the internal voltage regulator. vdd_p r1 47k rf_in_out note: filter is not required to meet bt and fcc specifications but may be added if better out-of-band performance is desired. c8 18pf c6 8.2pf vdd_p host interface l6 2.7nh c9 18pf l4 4.7nh c16 dni c17 dni in out fl1 shosin filter hmd846h 1 2 connect d[9] to d[10] to select internal rom mode. r4 10k c2 1uf l2 3.3nh c18 0.1uf y1 xtl 32mhz 1 3 c14 22pf r3 100k l3 3.9nh vbatt c13 1.8pf c15 180pf c7 8.2pf r5 10k c21 0.1uf c12 2.7pf
17 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds i/o configuration (top view) siw3000 top view vcc k2 k3 k4 k5 k6 k7 k8 k9 k1 k10 k11 a2 a3 a4 a5 a6 a7 a8 a9 b1 b3 b10 c1 c2 d1 d2 e1 e2 f1 f2 g1 g2 h1 h2 j1 j3 j4 j5 j6 j7 j8 j10 c9 c10 d9 d10 e9 e10 f9 f10 g9 g10 h9 h10 b2 b9 j2 j9 a1 a10 b11 j11 c11 d11 e11 f11 g11 h11 a11 c3 d3 e3 f3 g3 h3 l2 l3 l4 l5 l6 l7 l8 l9 l1 l10 l11 b4 b5 b6 b7 b8 c4 c5 c6 c7 c8 vcc rf_in gnd rf_out gnd vtune xtal_n a[15] vdd_c oe_n a[7] idac gnd gnd gnd gnd vcc xtal_p/clk pio[1] fcs_n d[12] d[15] vrefp_cap vrefn_cap gnd vcc vcc reset_n vss_p vss_c a[13] d[14] d[13] pwr_reg_en/ pio[8] host_ wakeup a[17]/ eeprom_scl uart_rts pcm_clk d[11] a[16]/ eeprom_sda a[14] a[12] d[9] pcm_sync d[10] chp_pump gnd ext_wake a[5] pcm_out vdd_p gnd vcc a[3] pcm_in a[4] vcc_out gnd vbatt_ana a[1] d[6]/pio[6] a[2] a b c d e f g h j l k 1234567891011 power rf ground a[18] d[4]/pio[4] d[5]/pio[5] a[8] vdd_p vdd_c a[6] vbatt_dig vss_usb vdd_usb clk32k_out a[11] d[8]/pio[3] d[2] d[3] vss_p vss_c a[9] usb_dpls_ pullup tx_rx_switch pio[2] d[7]/pio[7] d[0] d[1] uart_txd a[10] pio[0] uart_cts uart_rxd usb_dmns usb_dpls clk32k_in we_n/ eeprom_wp digital ground
18 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds packaging and product marking package drawing 96-pin, 6 mm x 6 mm, vfbga drawing and dimensions symbol min max notes: a 0.8 1.0 1. dimension b is measured at the maximum solder ball diameter, a1 0.2 0.3 parallel to datum plane z. a2 0.22 ref 2. datum z is defined by the spherical crowns of the a3 0.45 ref solder balls. b 0.25 0.35 3. parallelism measurem ent shall exclude any effect of d 6 bsc mark on top surface of package. e 6 bsc 4. all dimensions are in millimeters. e 0.5 bsc d1 5 bsc e1 5 bsc
19 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds package drawing 96-pin, 10 mm x 10 mm, lfbga drawing and dimensions symbol min max notes: a - 1.4 1. dimension b is measured at the maximum solder ball diameter, a1 0.27 0.37 parallel to datum plane z. a2 0.26 ref 2. datum z is defined by the spherical crowns of the a3 0.8 ref solder balls. b 0.35 0.45 3. parallelism measurem ent shall exclude any effect of d 10 bsc mark on top surface of package. e 10 bsc 4. all dimensions are in millimeters. e 0.8 bsc 5. dimensions and tolerances: asme y14.5m. d1 8 bsc 6. reference document: jedec-mo-210. e1 8 bsc
20 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds product marking tape and reel specification carrier tape: adv ml0707-a reel type: klik reel (16 mm) 13" dia. qty/reel 2500 peel test: 20?80 grams cover tape: rs standard (anti-static) leader: 500 mm (minimum 400 mm) trailer: 250 mm (minimum 160 mm) peel speed: 300 mm/minute note : drawing not to scale. siw3000aip1 lllll yyww arm 3000gip1 lllll yyww arm siw pin 1 corner 4 digit date code trace code 6-by-6-mm vfbga 10-by-10-mm lfbga
21 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds tape detail (6 mm x 6 mm vfbga) note: 1. tolerances 0.10 unless otherwise specified. 2. 10 sprocket hole pitch cumulative tolerance 0.2 3. camber not to exceed 1mm in 100 mm. 4. material: black advantek polystyrene. 5. ao and bo measured on a plane 0.3 mm above the bottom of the pocket. 6. ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier. 7. pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. 8. all dimensions in millimeters. direction of feed 0.25 16 0.3 section b-b ao= 6.30 mm bo= 6.30 mm ko= 1.50 mm section a-a r0.30 (typ.) ko a b see note 1 see note 6 a b 4.0 1.50 2.0 1.50 (min) 1.75 bo ao 12.0 r0.25 +0.1 0.0 0.30 0.05 7.5 see note 6
22 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds reel dimensions: klik reel note: all dimensions in millim eters (mm) unless otherwise stated. tape width a b(min) c d (min) n (min) w1 w2 (max) w3 (min) w3 (max) 16 330 1.50 13.00+0.5 20.20 100 16.4+2.0 -0.00 22.40 15.90 19.40
23 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds ordering information part number operational temperature range 1 package ordering quantity siw3000gip1 industrial 96-pin vfbga 6-by-6-mm 429 pcs. per tray siw3000gip1-t13 industrial 96-pin vfbga 6-by-6-mm 2500 on 13? reel siw3000gig1 industrial 96-pin vfbga 6-by-6-mm green 429 pcs. per tray SIW3000GIG1-T13 industrial 96-pin vfbga 6-by-6-mm green 2500 on 13? reel siw3000aip1 industrial 96-pin lfbga 10-by-10-mm 360 pcs. per tray siw3000aip1-t13 industrial 96-pin lfbga 10-by-10-mm 1500 on 13? reel 1 industrial temperature range: -40c to +85c
24 of 24 siw3000 60 0049 r01drf siw3000 radio processor ds rf micro devices believes the furnished information is correct and accurate at the time of this printing. rf micro devices reserves the right to make changes to its products without notice and advises customers to verify that the information being used is current. the described products are not designed, manufactured or intended for use in equipment for medical, life support, aircraft control or navigation, or any other applications that require failsafe operation. rf micro devices does not assume responsibility for the use of the described products. rf micro devices?, rfmd?, providing communication solutions?, the diamond logo design, silicon wave, and the siw product name prefix are trademarks of rfmd, llc. bluetooth? is a trademark owned by bluetooth sig, inc., u.s.a. and licensed for use by rf micro devices, inc. manufactured under license from arm limited. arm, arm7tdmi and the arm logo are the registered trademarks of arm limited in the eu and other countries. all other product, service, and company names are trademarks, registered trademarks or service marks of their respective owners.

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